Data representation and computer logic

CPU components and their interactions

The role of a GPU

CPU and GPU design and cooperation

Primary memory and processor performance

The fetch, decode and execute cycle

Pipelining across processor cores

Internal and external secondary storage

Lossless and lossy compression

Cloud computing service models

The **central processing unit (CPU)** carries out program instructions. To describe how it works, you need to explain each component’s role and trace how instructions, data and control signals move between components.

### Processing and control units
The **arithmetic logic unit (ALU)** performs arithmetic calculations and logical operations. It can add values or compare them. It also applies Boolean operations.

Instruction processing is coordinated by the **control unit (CU)**. It interprets instructions, then sends control signals to direct data transfers and operations in the processor.

The ALU doesn't choose its next operation independently. The CU directs it according to the current instruction.

### Registers
**Registers** are small, fast storage locations within the CPU. Each register below has a specific job.

| Register | Function |
|---|---|
| Instruction register (IR) | Holds the instruction currently being decoded or executed. |
| Program counter (PC) | Holds the address of the next instruction to be fetched. |
| Memory address register (MAR) | Holds the address of the memory location being accessed. |
| Memory data register (MDR) | Holds data or an instruction being transferred to or from memory. |
| Accumulator (AC) | Holds intermediate arithmetic or logic results in an accumulator-based processor. |

An address identifies a memory location, not the value stored there. The MAR holds that location; the MDR holds the contents being transferred.

### Buses
A **bus** is a communication pathway that carries signals between computer components.

| Bus | What it carries | Typical direction when accessing memory |
|---|---|---|
| Address bus | The address of the location to access | CPU to memory |
| Data bus | Instructions and data | Either direction |
| Control bus | Signals that coordinate operations, including memory read and memory write | Depends on the signal |

The relationship diagram shows the CPU connected to main memory through the address bus, data bus and control bus. Inside the CPU, the PC supplies an instruction address to the MAR. A fetched instruction passes from the MDR to the IR, which the CU interprets. The CU directs the ALU, and the ALU uses the AC for intermediate results.
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Suppose an instruction needs a value from memory. The CPU places the value’s address in the MAR, and the address bus carries it to memory. The CU issues a memory read signal on the control bus. The value then returns along the data bus into the MDR, ready for the processor to use.

### Processor arrangements
A **core** is a processing unit capable of executing instructions.

| Processor arrangement | Description |
|---|---|
| Single core processor | Contains one core, which executes an instruction stream. |
| Multi-core processor | Contains multiple cores that can execute separate instruction streams concurrently. To gain the full benefit, software must provide work that can be divided between the cores. |
| Co-processor | An additional processor that assists the main CPU by handling a particular category of work. |

Adding cores doesn't automatically make every program proportionally faster. If a task’s steps depend on previous results, those steps cannot simply be split into independent pieces.

**Terms:** arithmetic logic unit (ALU), control unit (CU), instruction register (IR), program counter (PC), memory address register (MAR), memory data register (MDR), accumulator (AC), address bus, data bus, control bus, single core processor, multi-core processor, co-processors.

CPU relationship flow showing the program counter (PC), memory address register (MAR), memory data register (MDR), instruction register (IR), control unit (CU), arithmetic logic unit (ALU), accumulator (AC) and main memory. The PC supplies an instruction address to the MAR, and the address bus carries it to main memory. The CU sends memory read and memory write signals on the control bus. Data travels on the data bus in both directions between main memory and the MDR. A fetched instruction passes from the MDR to the IR, and the CU interprets it. The CU directs the ALU, which uses the AC for intermediate results. The PC connects only to the MAR, and the AC connects only to the ALU.

A **graphics processing unit (GPU)** is a processor designed to perform large numbers of similar calculations in parallel. It produces graphics and accelerates other computational tasks when their patterns of work suit parallel processing.

### Architecture suited to parallel work
Inside a GPU, many processing cores carry out similar operations on different data items. They can process many items at once rather than completing every calculation one after another.

This design works particularly well when a large problem can be split into many similar calculations with limited dependence between them. The calculations need large volumes of data; high memory bandwidth helps supply it.

In the figure, input data is divided into independent groups. GPU cores process these groups in parallel before the results are combined into an output. What matters is the repeated operation across many data items, not simply the size of the problem.
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### Applications
Producing each frame of a video game requires colour calculations for many pixels. A GPU performs these in parallel, helping the system render detailed scenes quickly enough for smooth movement.

Training a machine learning model often involves repeating the same kinds of numerical operations across large collections of values. When the workload is suitable, a GPU can perform many of these calculations simultaneously and reduce processing time.

GPUs have other applications wherever work can be organised into large groups of similar calculations. A task with frequent decisions or a chain of dependent steps, though, may make poor use of the GPU's parallel architecture.

**Terms:** graphics processing unit (GPU), parallel processing, graphics rendering, machine learning.

Parallel-work schematic arranged left to right: input data, independent groups, GPU cores performing a repeated operation in parallel, and combined output. Use repeated unlabeled core shapes within the GPU cores group to communicate concurrency without implying a particular core count.

A CPU and a GPU differ because they are designed for different priorities. The CPU handles varied instructions flexibly and with low latency. The GPU aims for high throughput when many similar calculations can run in parallel.

### Design choices and their consequences
**Latency** is the time needed to complete an individual operation or task. **Throughput** measures how much work is completed in a given time.

| Aspect | CPU | GPU |
|---|---|---|
| Design philosophy | Complete varied tasks responsively, including those that involve many decisions. | Complete large amounts of similar work in parallel. |
| Core architecture | Typically has fewer, more complex cores with substantial control capabilities. | Typically has many simpler processing cores organised for parallel work. |
| Processing power | Handles sequential work and branching effectively, along with general-purpose control. | Delivers high total computational throughput for suitable parallel workloads. |
| Memory access | Uses caches to reduce delays when accessing frequently needed data and handles varied access patterns well. | Emphasises high-bandwidth access to large quantities of data; benefits when parallel operations access that data in an organised pattern. |
| Power efficiency | Often more efficient for small, sequential or control-heavy tasks. | Can use less energy per calculation for suitable parallel calculations, although total power consumption may be high. |
| Usage scenarios | Running application control logic and processing tasks whose steps depend on earlier steps. | Graphics rendering and large batches of numerical calculations. |

A GPU isn't simply a faster CPU. When one calculation must wait for the previous result, many GPU cores may sit unused. A CPU, meanwhile, may take longer to process a huge batch of independent calculations because it has fewer parallel processing resources.

### Working together
Consider a system that analyses images for damaged parcels. Incoming images are managed by the CPU, which decides which batch is ready. The GPU then performs repeated numerical calculations across that batch. Once the results return, the CPU uses them to decide which parcels need inspection.

The cooperation diagram separates task division from data sharing and coordinating execution. It shows CPU preparation followed by data sharing, then GPU computation, returned results and CPU follow-up.
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**Task division** assigns control-heavy work to the CPU and suitable parallel calculations to the GPU. Each processor can then handle work that suits its architecture.

**Data sharing** makes inputs and results available to both processors. Separate CPU and GPU memory can require data transfers between them; other systems allow access to shared memory. Those transfers take time. For a very small task, moving it to a GPU may cost more time than the computation saves.

**Coordinating execution** ensures that the GPU starts only once its inputs are ready and that the CPU waits until the GPU finishes before using its results. While GPU processing continues, the CPU may carry out other independent work.

**Terms:** CPU, GPU, core architecture, processing power, memory access, power efficiency, task division, data sharing, coordinating execution.

CPU–GPU cooperation flow for damaged-parcel image analysis. Arrange CPU preparation, data sharing, GPU computation, returned results and CPU follow-up in order. Group preparation and follow-up under CPU and numerical batch processing under GPU. Add relationships labelled task division and coordinating execution, showing that inputs must be ready before GPU computation and results ready before CPU follow-up.

Primary memory holds the instructions and data needed during processing. Each form makes a different trade-off between speed, capacity and persistence. Very fast storage has limited capacity; larger working memory takes longer to access.

### Purposes of the different types
**Random-access memory (RAM)** holds the programs and data currently in use and allows both reading and writing. It is volatile: remove the power, and its contents are lost.

**Read only memory (ROM)** keeps its contents when power is removed, so it is non-volatile. During ordinary operation, those contents are normally read rather than changed. ROM stores persistent instructions, such as those needed to begin the computer's startup process.

**Cache** is small, fast memory that holds copies of instructions and data the CPU is likely to need. With these copies close at hand, the CPU needs fewer slower accesses to RAM.

**Registers** are small storage locations inside the CPU. They hold values immediately involved in processing, giving direct access to the current instruction, memory addresses and intermediate results.

| Memory type | Main purpose | Performance significance |
|---|---|---|
| Registers | Hold the CPU's immediate working values | Fastest access, but extremely limited capacity |
| L1 cache | Keep a small collection of instructions and data very close to a core | Usually the smallest and fastest cache level |
| L2 cache | Hold more cached instructions and data than L1 | Usually larger but slower than L1 |
| L3 cache | Provide a larger final cache level, often shared by cores | Usually larger but slower than L2 |
| RAM | Hold active programs and their working data | Much greater capacity than cache, but slower to access |
| ROM | Preserve startup instructions when power is off | Persistence, rather than fast working storage, is its central purpose |

### How the hierarchy improves performance
The memory hierarchy figure runs from registers through L1 cache, L2 cache and L3 cache to RAM: from the CPU's fastest, smallest working storage towards larger, slower storage. ROM sits separately. Its main role is to preserve instructions, not to act as another cache level.
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If a nearby cache already holds the required instructions or data, the CPU can retrieve them without waiting for RAM. Keeping frequently reused information close to the processor cuts average access time.

A **cache hit** occurs when the cache being checked contains the requested instruction or data. If it doesn't, a **cache miss** occurs.

Missing an item in L1 does not necessarily require an access to RAM. L2 or L3 may hold it instead. Only when the item is absent from all relevant cache levels must it be obtained from RAM; a copy can then be placed in cache for later use.

For example, repeated use of the same small group of values may lead to many cache hits after the first access. The processor spends less time waiting for memory, improving performance.

**Terms:** random-access memory (RAM), read only memory (ROM), cache, L1, L2, L3, registers, cache hit, cache miss.

Memory hierarchy showing registers, L1 cache, L2 cache, L3 cache and RAM in that order, with opposing arrows for faster access and greater capacity. Place ROM separately, labelled persistent startup instructions. Show a cache hit supplying the requested item and a cache miss leading towards the next cache level or RAM.

The CPU repeats the **fetch, decode and execute cycle** to obtain a machine-language instruction, interpret it and carry out its operation. As the instruction passes through the cycle, register contents and bus signals change.

### Fetch
The PC holds the address of the next instruction. To begin the fetch, the CPU copies that address into the MAR. The MAR then places it on the address bus.

A memory read signal travels from the CU along the control bus. Memory sends the instruction back along the data bus into the MDR. From there, the CPU copies it into the IR.

During the fetch process, the PC advances to the next instruction address. It now points ahead; the IR still holds the instruction being processed.

### Decode
The CU interprets the instruction held in the IR, identifying the operation to perform and determining which operands or memory locations are involved.

An **operand** is a value, or a reference to a value, on which an instruction operates. For example, an instruction might specify addition as the operation and give the location of the value to add.

### Execute
The CU sends signals that carry out the operation. For an arithmetic instruction, this may involve using the ALU and placing the result in the AC. A memory instruction may read or write data. A branch instruction, by contrast, may replace the PC's value with a different instruction address.

In the cycle figure, the main path runs from PC to MAR, memory, MDR and IR, then through CU decoding and execution. The figure also shows that execution may need another memory access.
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### A worked instruction cycle
Suppose the PC contains address 20 and the AC contains 5. Address 20 stores an instruction to add the value at address 60, which contains 3. In this example, consecutive instruction addresses differ by one.

| Stage | Register and bus activity |
|---|---|
| Fetch address | Copy 20 from PC to MAR; the address bus carries 20. |
| Fetch instruction | CU sends a memory read signal on the control bus. The instruction returns on the data bus into MDR, then moves to IR. PC advances to 21. |
| Decode | CU interprets the instruction as adding the contents of address 60 to AC. |
| Fetch operand | MAR receives 60. A memory read returns 3 through the data bus into MDR. |
| Execute addition | ALU adds the AC value 5 and the fetched value 3; AC becomes 8. |

If an instruction writes a result to memory instead, the MAR holds the destination address and the MDR holds the value. The CU sends a memory write signal, and the data bus carries the value from the CPU to memory.

**Terms:** fetch, decode, execute, machine language, program counter (PC), memory address register (MAR), memory data register (MDR), instruction register (IR), accumulator (AC), control unit (CU), arithmetic logic unit (ALU), address bus, data bus, control bus.

Fetch–decode–execute flowchart. Fetch: the address is copied from the PC into the MAR, and the MAR places it on the address bus to memory. The CU sends a memory read signal along the control bus. Memory returns the instruction along the data bus into the MDR, and the instruction is then copied into the IR. Meanwhile the PC advances to the next instruction address. Decode: the CU interprets the instruction held in the IR. Execute: the CU may use the ALU for an arithmetic instruction and place the result in the AC. It may make a memory read or write, with read data returning through the MDR. For a branch, it replaces the PC's value with a new instruction address.

**Pipelining** lets a processor core overlap different stages of several instructions. In a multi-core processor, each core can run its own pipeline while other cores handle separate instruction streams in parallel.

### The four stages
| Stage | Work performed |
|---|---|
| Fetch | Get the next instruction from memory. |
| Decode | Interpret the instruction and identify the required operation and operands. |
| Execute | Perform the operation, such as an ALU calculation. |
| Write-back | Put the result in its destination register; an instruction that writes memory must also complete the required memory write. |

Each stage uses different parts of the processor. As soon as an instruction leaves the fetch stage, the fetch hardware can start obtaining the next instruction. It doesn't have to wait for the earlier instruction to finish completely.

### Overlapping instructions
Suppose each stage in an idealised pipeline takes one clock cycle. Instruction A is fetched in cycle 1, decoded in cycle 2, executed in cycle 3 and written back in cycle 4. B starts one cycle later: fetch in cycle 2, decode in cycle 3, execute in cycle 4 and write-back in cycle 5.

The timeline shows how these stages overlap on core 1. At the same time, core 2 processes instruction C on the same schedule as A and instruction D on the same schedule as B. The two cores progress independently as well as in parallel.
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Without overlap, one core would take eight stage-length cycles to complete two instructions. In this idealised pipeline, A and B finish in five cycles. Each instruction still goes through all four stages. Pipelining improves throughput; it doesn't remove stages from an instruction.

### Pipelining and multiple cores are different
Pipelining overlaps stages within a core, whereas multiple cores let separate instruction streams execute at the same time. When there is enough suitable work, a multi-core processor can benefit from both.

Not every program will see these gains. Processing may have to wait if an instruction needs a result that isn't ready. And if the available work cannot be divided into independent tasks, the cores cannot all contribute effectively.

**Terms:** pipelining, fetch, decode, execute, write-back, multi-core processor, independently, in parallel, throughput.

Pipeline timing diagram with cycles 1 through 5 horizontally and separate groups for core 1 and core 2. Core 1 has instruction A using fetch, decode, execute and write-back in consecutive cycles starting in cycle 1, and instruction B starting in cycle 2. Core 2 repeats those schedules for instruction C and instruction D respectively. Highlight simultaneous stages within each core and simultaneous work between the cores.

**Secondary storage** retains programs and data beyond the current processing session and is non-volatile. Internal storage sits within a device. External storage is accessed through an external connection or a network.

### Internal storage
| Type | How it stores data | Characteristics and suitable use |
|---|---|---|
| Solid state drive (SSD) | Stores data in flash memory, with no moving mechanical parts. | Fast access and resistance to movement suit a portable computer's operating system, applications and active files. An SSD generally costs more per unit of capacity than an HDD. |
| Hard disk drive (HDD) | Records data magnetically on rotating platters; moving read/write heads access it. | Its large capacity and relatively low cost suit a desktop that stores a substantial media collection. Moving mechanical parts slow access and make it more vulnerable to physical shocks. |
| Embedded multimedia card (eMMC) | Combines flash storage and a controller in a package normally attached to the device's circuit board. | This compact, inexpensive storage suits a basic tablet or embedded device. It is generally slower than an SSD and is not normally user-replaceable. |

### External storage
SSD and HDD name storage technologies, not just internal devices. Either can go in an external enclosure. In the figure, internal storage includes SSD, HDD and eMMC; external storage includes SSD, HDD, optical drives, flash drives, memory cards and network attached storage.
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| Type | Characteristics | Suitable scenario |
|---|---|---|
| External SSD | Fast flash storage with no moving parts; usually relatively expensive per unit of capacity. | Moving a large active video project between workstations. |
| External HDD | Offers high-capacity magnetic storage at relatively low cost, but is less resistant to knocks. | Keeping a large local backup collection. |
| Optical drive | Reads or writes optical discs using a laser; the drive and disc must be compatible. | Reading supplied disc-based material or distributing files on physical discs. |
| Flash drive | A small flash-storage device that commonly connects through USB. | Carrying a modest set of documents between computers. |
| Memory card | Small, removable flash storage; its format must match the device. | Storing images in a camera and transferring them to a computer. |
| Network attached storage (NAS) | A storage device or system that provides access to files over a network. | Providing shared files and a central backup destination for several computers. |

### Choosing storage for a situation
To choose suitable storage, consider capacity and access speed alongside cost, portability, durability and compatibility. Frequent work on large files may call for an external SSD. When capacity matters more than speed, an external HDD may be more economical.

Unlike a directly attached drive, NAS relies on the network as well as the storage hardware for access. It may contain HDDs or SSDs. Several users can access the shared storage without passing a physical drive between computers.

**Terms:** secondary storage, internal, external, solid state drive (SSD), hard disk drive (HDD), embedded multimedia card (eMMC), optical drive, flash drive, memory card, network attached storage (NAS).

Top-down storage classification tree. Secondary storage branches into internal storage (within a device) and external storage (accessed through an external connection or a network). Internal storage leads to solid state drive (SSD), hard disk drive (HDD) and embedded multimedia card (eMMC). External storage leads to the same SSD and HDD nodes (in an external enclosure), so those two technologies appear in both categories. External storage also leads to optical drive, flash drive (USB) and memory card through an external connection, and to network attached storage (NAS) through network access. That keeps the NAS route separate from the directly connected devices.

**Compression** uses fewer bits to represent data than the original representation. It can save storage space and reduce the amount of data that must be transmitted, though encoding and decoding require processing.

### Lossless and lossy methods
**Lossless compression** allows the original data to be reconstructed exactly. Use it when any change to the contents would be unacceptable—for example, in a program or a collection of financial records.

**Lossy compression** discards some information, so decompression cannot reproduce the original exactly. For media, some loss of detail may be acceptable in return for a smaller file.

| Aspect | Lossless | Lossy |
|---|---|---|
| Recovery | Exact reconstruction | Approximate reconstruction |
| Main approach | Encode patterns or redundancy more efficiently | Remove selected information as well as encode efficiently |
| Suitable data | Programs, records and other data requiring exact preservation | Images, audio or video where some quality loss is acceptable |
| Main limitation | The reduction depends on patterns in the original data | Greater reduction can cause more noticeable quality loss |

### Run-length encoding
**Run-length encoding (RLE)** replaces a sequence of repeated identical values with a value and its repetition count. The count tells the decoder exactly how many copies to restore, making this a lossless method.

Take the sequence AAAAABBCCCC. With the count followed by the symbol, five copies of A become 5A. Two copies of B give 2B, and four copies of C give 4C. Together, these produce the encoded form 5A2B4C.

| Run | Symbol | Count | Encoded form |
|---|---|---|---|
| First | A | 5 | 5A |
| Second | B | 2 | 2B |
| Third | C | 4 | 4C |

To decode, expand each pair: 5A becomes AAAAA, 2B becomes BB, and 4C becomes CCCC. Joining these runs restores AAAAABBCCCC exactly.

Suppose each symbol and each single-digit count occupies one byte in this example. The original then uses 11 bytes, compared with 6 bytes for the encoded version, excluding any additional format information. RLE works well with long runs. But under the same representation, ABCD would become 1A1B1C1D—a larger sequence.

### Transform coding
**Transform coding** changes a block of data into coefficients that describe its component patterns. In this representation, important information can be concentrated into a smaller number of significant coefficients.

When transform coding is used for lossy compression, the encoder rounds coefficients or removes less significant ones. This step is called **quantization**, and it loses information. The remaining values are then encoded. During decoding, an inverse transform reconstructs an approximation.

The process figure follows original data, transform, coefficients, quantization, encoding, compressed data, decoding, inverse transform and reconstructed approximation. Information is lost during quantization, not simply because the data was transformed.
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For an image, keeping broad changes in colour while reducing fine detail can produce a smaller file that still looks similar to the original. Removing more may shrink the file further, but the lost detail can become more visible.

**Terms:** compression, lossless compression, lossy compression, run-length encoding, transform coding.

Transform-coding flowchart ordered original data, transform, coefficients, quantization, encoding, compressed data, decoding, inverse transform, reconstructed approximation. Mark quantization as the information-loss step and use a comparison connection between original data and reconstructed approximation to show that exact recovery is not possible after that loss.

**Cloud computing** gives users access to computing resources over a network. A service provider manages those resources. SaaS, PaaS and IaaS differ mainly in what the provider supplies and what the customer has to manage.

### The three service models
With **Software as a service (SaaS)**, the customer accesses a ready-to-use application over a network. They use and configure it; they don't maintain the underlying software platform or hardware.

**Platform as a service (PaaS)** gives customers a managed environment for developing and running their own applications. The provider maintains the underlying infrastructure, operating system and application runtime.

For customers who need computing infrastructure, **Infrastructure as a service (IaaS)** supplies resources such as virtual machines, storage and networking. The customer manages the operating system and any software installed on those resources.

| Model | Provider manages | Customer manages | Example situation |
|---|---|---|---|
| SaaS | Application, platform and infrastructure | Data, user access and available application settings | A community centre uses an online booking application without developing its own software. |
| PaaS | Platform and infrastructure | Application code, application configuration and data | A development team deploys its own appointment application without maintaining the server operating system. |
| IaaS | Underlying physical infrastructure and virtual resource provision | Operating system, runtime, applications and data | An organisation creates a custom server environment requiring particular operating-system settings. |

The responsibility diagram shows layers for application, runtime, operating system and infrastructure. Moving from SaaS through PaaS to IaaS, the customer takes responsibility for more layers. That gives them greater control, but also more management work.
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### Control, flexibility and resource management
SaaS needs the least technical administration. The customer is, however, limited to the provider's application features and configuration options. It suits organisations that want to use a service rather than build one.

Developers using PaaS control their own application without having to handle much of the underlying maintenance. The trade-off is that they depend on the runtimes, tools and resource options the platform supports.

IaaS offers greater flexibility over the software environment. With that control comes responsibility: the customer must handle tasks such as updating the operating system, configuring software and allocating the supplied resources effectively.

### Resource availability
Customers can often increase or reduce cloud resources without buying physical equipment. How they do this depends on the model. A SaaS customer may change a subscription or user allowance; a PaaS customer may change application capacity. An IaaS customer may provision additional virtual machines or storage.

Being in the cloud does not make availability unlimited or guaranteed. Access depends on network connectivity and provider operation, as well as service limits and the resources included in the customer's plan. Greater customer control does not automatically give greater availability: customers must also manage the resources they are responsible for.

**Terms:** software as a service (SaaS), platform as a service (PaaS), infrastructure as a service (IaaS), control, flexibility, resource management, resource availability.

Three-column responsibility diagram labelled SaaS, PaaS and IaaS, each with layers application, runtime, operating system and infrastructure. Use provider and customer responsibility categories: provider manages all four layers for SaaS; customer manages application for PaaS; customer manages application, runtime and operating system for IaaS. Note alongside all models that customers manage data and user access. Show increasing customer control and management work from SaaS to IaaS.

State one register involved in fetching an instruction from primary memory.

State two functions of the control unit (CU).

State one characteristic of random-access memory (RAM).

Explain how a cache hit can improve the performance of an animation application running on a workstation.

Compare the use of an internal solid state drive (SSD) with an internal hard disk drive (HDD) in an artist's workstation.

Explain why a GPU is suitable for rendering the frames of an animation.

State one computing resource that can be supplied through infrastructure as a service (IaaS).

State two aspects of a system that the association would control when using platform as a service (PaaS).

State one benefit to the association of using software as a service (SaaS) for its booking system.

Explain why SaaS may be less flexible than PaaS if the association requires a new, specialized waiting-list feature.

Distinguish between SaaS, PaaS and IaaS in terms of the control and resource-management responsibility retained by the association.

Explain why IaaS may be appropriate for the association's future real-time attendance analysis system if it requires a particular operating-system and network configuration.

State one performance benefit of cache memory.

Explain why the GPU is suitable for updating the map cells in the simulation.

State two features of pipelining in a multi-core processor.

Distinguish between the core architectures of a CPU and a GPU by stating two differences.

Explain how the CPU and GPU could work together to carry out the simulation.

Computer Science

IB Computer Science focuses on computational thinking and programming skills. Students learn about system fundamentals, network architecture, and software development, applying their knowledge to solve real-world problems through practical projects.

A1.1 Computer hardware and operation

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