The central processing unit (CPU) carries out program instructions. To describe how it works, you need to explain each component’s role and trace how instructions, data and control signals move between components.

Processing and control units

The arithmetic logic unit (ALU) performs arithmetic calculations and logical operations. It can add values or compare them. It also applies Boolean operations.

Instruction processing is coordinated by the control unit (CU). It interprets instructions, then sends control signals to direct data transfers and operations in the processor.

The ALU doesn't choose its next operation independently. The CU directs it according to the current instruction.

Registers

Registers are small, fast storage locations within the CPU. Each register below has a specific job.

An address identifies a memory location, not the value stored there. The MAR holds that location; the MDR holds the contents being transferred.

Buses

A bus is a communication pathway that carries signals between computer components.

Suppose an instruction needs a value from memory. The CPU places the value’s address in the MAR, and the address bus carries it to memory. The CU issues a memory read signal on the control bus. The value then returns along the data bus into the MDR, ready for the processor to use.

Processor arrangements

A core is a processing unit capable of executing instructions.

Adding cores doesn't automatically make every program proportionally faster. If a task’s steps depend on previous results, those steps cannot simply be split into independent pieces.

Terms: arithmetic logic unit (ALU), control unit (CU), instruction register (IR), program counter (PC), memory address register (MAR), memory data register (MDR), accumulator (AC), address bus, data bus, control bus, single core processor, multi-core processor, co-processors.

A graphics processing unit (GPU) is a processor designed to perform large numbers of similar calculations in parallel. It produces graphics and accelerates other computational tasks when their patterns of work suit parallel processing.

Architecture suited to parallel work

Inside a GPU, many processing cores carry out similar operations on different data items. They can process many items at once rather than completing every calculation one after another.

This design works particularly well when a large problem can be split into many similar calculations with limited dependence between them. The calculations need large volumes of data; high memory bandwidth helps supply it.

Applications

Producing each frame of a video game requires colour calculations for many pixels. A GPU performs these in parallel, helping the system render detailed scenes quickly enough for smooth movement.

Training a machine learning model often involves repeating the same kinds of numerical operations across large collections of values. When the workload is suitable, a GPU can perform many of these calculations simultaneously and reduce processing time.

GPUs have other applications wherever work can be organised into large groups of similar calculations. A task with frequent decisions or a chain of dependent steps, though, may make poor use of the GPU's parallel architecture.

Terms: graphics processing unit (GPU), parallel processing, graphics rendering, machine learning.

A CPU and a GPU differ because they are designed for different priorities. The CPU handles varied instructions flexibly and with low latency. The GPU aims for high throughput when many similar calculations can run in parallel.

Design choices and their consequences

Latency is the time needed to complete an individual operation or task. Throughput measures how much work is completed in a given time.

A GPU isn't simply a faster CPU. When one calculation must wait for the previous result, many GPU cores may sit unused. A CPU, meanwhile, may take longer to process a huge batch of independent calculations because it has fewer parallel processing resources.

Working together

Consider a system that analyses images for damaged parcels. Incoming images are managed by the CPU, which decides which batch is ready. The GPU then performs repeated numerical calculations across that batch. Once the results return, the CPU uses them to decide which parcels need inspection.

Task division assigns control-heavy work to the CPU and suitable parallel calculations to the GPU. Each processor can then handle work that suits its architecture.

Data sharing makes inputs and results available to both processors. Separate CPU and GPU memory can require data transfers between them; other systems allow access to shared memory. Those transfers take time. For a very small task, moving it to a GPU may cost more time than the computation saves.

Coordinating execution ensures that the GPU starts only once its inputs are ready and that the CPU waits until the GPU finishes before using its results. While GPU processing continues, the CPU may carry out other independent work.

Terms: CPU, GPU, core architecture, processing power, memory access, power efficiency, task division, data sharing, coordinating execution.

Primary memory holds the instructions and data needed during processing. Each form makes a different trade-off between speed, capacity and persistence. Very fast storage has limited capacity; larger working memory takes longer to access.

Purposes of the different types

Random-access memory (RAM) holds the programs and data currently in use and allows both reading and writing. It is volatile: remove the power, and its contents are lost.

Read only memory (ROM) keeps its contents when power is removed, so it is non-volatile. During ordinary operation, those contents are normally read rather than changed. ROM stores persistent instructions, such as those needed to begin the computer's startup process.

Cache is small, fast memory that holds copies of instructions and data the CPU is likely to need. With these copies close at hand, the CPU needs fewer slower accesses to RAM.

Registers are small storage locations inside the CPU. They hold values immediately involved in processing, giving direct access to the current instruction, memory addresses and intermediate results.

How the hierarchy improves performance

If a nearby cache already holds the required instructions or data, the CPU can retrieve them without waiting for RAM. Keeping frequently reused information close to the processor cuts average access time.

A cache hit occurs when the cache being checked contains the requested instruction or data. If it doesn't, a cache miss occurs.

Missing an item in L1 does not necessarily require an access to RAM. L2 or L3 may hold it instead. Only when the item is absent from all relevant cache levels must it be obtained from RAM; a copy can then be placed in cache for later use.

For example, repeated use of the same small group of values may lead to many cache hits after the first access. The processor spends less time waiting for memory, improving performance.

Terms: random-access memory (RAM), read only memory (ROM), cache, L1, L2, L3, registers, cache hit, cache miss.

The CPU repeats the fetch, decode and execute cycle to obtain a machine-language instruction, interpret it and carry out its operation. As the instruction passes through the cycle, register contents and bus signals change.

Fetch

The PC holds the address of the next instruction. To begin the fetch, the CPU copies that address into the MAR. The MAR then places it on the address bus.

A memory read signal travels from the CU along the control bus. Memory sends the instruction back along the data bus into the MDR. From there, the CPU copies it into the IR.

During the fetch process, the PC advances to the next instruction address. It now points ahead; the IR still holds the instruction being processed.

Decode

The CU interprets the instruction held in the IR, identifying the operation to perform and determining which operands or memory locations are involved.

An operand is a value, or a reference to a value, on which an instruction operates. For example, an instruction might specify addition as the operation and give the location of the value to add.

Execute

The CU sends signals that carry out the operation. For an arithmetic instruction, this may involve using the ALU and placing the result in the AC. A memory instruction may read or write data. A branch instruction, by contrast, may replace the PC's value with a different instruction address.

A worked instruction cycle

Suppose the PC contains address 20 and the AC contains 5. Address 20 stores an instruction to add the value at address 60, which contains 3. In this example, consecutive instruction addresses differ by one.

If an instruction writes a result to memory instead, the MAR holds the destination address and the MDR holds the value. The CU sends a memory write signal, and the data bus carries the value from the CPU to memory.

Terms: fetch, decode, execute, machine language, program counter (PC), memory address register (MAR), memory data register (MDR), instruction register (IR), accumulator (AC), control unit (CU), arithmetic logic unit (ALU), address bus, data bus, control bus.

Pipelining lets a processor core overlap different stages of several instructions. In a multi-core processor, each core can run its own pipeline while other cores handle separate instruction streams in parallel.

The four stages

Each stage uses different parts of the processor. As soon as an instruction leaves the fetch stage, the fetch hardware can start obtaining the next instruction. It doesn't have to wait for the earlier instruction to finish completely.

Overlapping instructions

Suppose each stage in an idealised pipeline takes one clock cycle. Instruction A is fetched in cycle 1, decoded in cycle 2, executed in cycle 3 and written back in cycle 4. B starts one cycle later: fetch in cycle 2, decode in cycle 3, execute in cycle 4 and write-back in cycle 5.

Without overlap, one core would take eight stage-length cycles to complete two instructions. In this idealised pipeline, A and B finish in five cycles. Each instruction still goes through all four stages. Pipelining improves throughput; it doesn't remove stages from an instruction.

Pipelining and multiple cores are different

Pipelining overlaps stages within a core, whereas multiple cores let separate instruction streams execute at the same time. When there is enough suitable work, a multi-core processor can benefit from both.

Not every program will see these gains. Processing may have to wait if an instruction needs a result that isn't ready. And if the available work cannot be divided into independent tasks, the cores cannot all contribute effectively.

Terms: pipelining, fetch, decode, execute, write-back, multi-core processor, independently, in parallel, throughput.

Secondary storage retains programs and data beyond the current processing session and is non-volatile. Internal storage sits within a device. External storage is accessed through an external connection or a network.

Internal storage

External storage

Choosing storage for a situation

To choose suitable storage, consider capacity and access speed alongside cost, portability, durability and compatibility. Frequent work on large files may call for an external SSD. When capacity matters more than speed, an external HDD may be more economical.

Unlike a directly attached drive, NAS relies on the network as well as the storage hardware for access. It may contain HDDs or SSDs. Several users can access the shared storage without passing a physical drive between computers.

Terms: secondary storage, internal, external, solid state drive (SSD), hard disk drive (HDD), embedded multimedia card (eMMC), optical drive, flash drive, memory card, network attached storage (NAS).

Compression uses fewer bits to represent data than the original representation. It can save storage space and reduce the amount of data that must be transmitted, though encoding and decoding require processing.

Lossless and lossy methods

Lossless compression allows the original data to be reconstructed exactly. Use it when any change to the contents would be unacceptable—for example, in a program or a collection of financial records.

Lossy compression discards some information, so decompression cannot reproduce the original exactly. For media, some loss of detail may be acceptable in return for a smaller file.

Run-length encoding

Run-length encoding (RLE) replaces a sequence of repeated identical values with a value and its repetition count. The count tells the decoder exactly how many copies to restore, making this a lossless method.

Take the sequence AAAAABBCCCC. With the count followed by the symbol, five copies of A become 5A. Two copies of B give 2B, and four copies of C give 4C. Together, these produce the encoded form 5A2B4C.

To decode, expand each pair: 5A becomes AAAAA, 2B becomes BB, and 4C becomes CCCC. Joining these runs restores AAAAABBCCCC exactly.

Suppose each symbol and each single-digit count occupies one byte in this example. The original then uses 11 bytes, compared with 6 bytes for the encoded version, excluding any additional format information. RLE works well with long runs. But under the same representation, ABCD would become 1A1B1C1D—a larger sequence.

Transform coding

Transform coding changes a block of data into coefficients that describe its component patterns. In this representation, important information can be concentrated into a smaller number of significant coefficients.

When transform coding is used for lossy compression, the encoder rounds coefficients or removes less significant ones. This step is called quantization, and it loses information. The remaining values are then encoded. During decoding, an inverse transform reconstructs an approximation.

For an image, keeping broad changes in colour while reducing fine detail can produce a smaller file that still looks similar to the original. Removing more may shrink the file further, but the lost detail can become more visible.

Terms: compression, lossless compression, lossy compression, run-length encoding, transform coding.

Cloud computing gives users access to computing resources over a network. A service provider manages those resources. SaaS, PaaS and IaaS differ mainly in what the provider supplies and what the customer has to manage.

The three service models

With Software as a service (SaaS), the customer accesses a ready-to-use application over a network. They use and configure it; they don't maintain the underlying software platform or hardware.

Platform as a service (PaaS) gives customers a managed environment for developing and running their own applications. The provider maintains the underlying infrastructure, operating system and application runtime.

For customers who need computing infrastructure, Infrastructure as a service (IaaS) supplies resources such as virtual machines, storage and networking. The customer manages the operating system and any software installed on those resources.

Control, flexibility and resource management

SaaS needs the least technical administration. The customer is, however, limited to the provider's application features and configuration options. It suits organisations that want to use a service rather than build one.

Developers using PaaS control their own application without having to handle much of the underlying maintenance. The trade-off is that they depend on the runtimes, tools and resource options the platform supports.

IaaS offers greater flexibility over the software environment. With that control comes responsibility: the customer must handle tasks such as updating the operating system, configuring software and allocating the supplied resources effectively.

Resource availability

Customers can often increase or reduce cloud resources without buying physical equipment. How they do this depends on the model. A SaaS customer may change a subscription or user allowance; a PaaS customer may change application capacity. An IaaS customer may provision additional virtual machines or storage.

Being in the cloud does not make availability unlimited or guaranteed. Access depends on network connectivity and provider operation, as well as service limits and the resources included in the customer's plan. Greater customer control does not automatically give greater availability: customers must also manage the resources they are responsible for.

Terms: software as a service (SaaS), platform as a service (PaaS), infrastructure as a service (IaaS), control, flexibility, resource management, resource availability.